Graduate SoC Physical Design Engineer

About the role

As a Graduate Physical Design Engineer you will join NXP’s advanced semiconductor team in Tianjin and take part in the full physical implementation flow of SoC and subsystem designs, from netlist to GDSII.

Key responsibilities

• Support SoC and subsystem physical design implementation, including floorplanning, power planning, placement, CTS, routing and chip finishing.
• Perform timing, power, signal‑integrity and physical verification analysis and debug implementation issues to meet PPAC targets.
• Collaborate with RTL, DFT, verification, IP, package and technology teams.
• Develop and improve EDA automation scripts using Python, Tcl or other scripting languages.
• Explore AI‑assisted design methodologies and contribute to continuous improvement of backend flows.
• Support silicon bring‑up, design reviews and tape‑out activities.

Required profile

• Master’s degree (expected 2027) in Microelectronics, IC Design, Electronic or Computer Engineering or related fields.
• Basic knowledge of VLSI design flow, semiconductor fundamentals and Linux/Unix environments.
• Strong analytical, problem‑solving, communication and teamwork skills.
• Fluent written and spoken English.

Required skills

• Programming/scripting: Python, Tcl, Perl, Shell, C/C++.
• EDA tools: Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, Tempus, Calibre.
• Familiarity with AI/ML applications in semiconductor design (optional but a plus).