Senior ASIC Verification Engineer – PMU
NVIDIA · Shanghai
Job description
About the role
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products, from data centers to automotive and personal computing. The PMU IP, built around a RISC‑V core and custom control logic, collects and processes data from the whole chip to determine optimal operating points. We are looking for a senior ASIC engineer to help architect the next‑generation PMU for AI datacenter applications.
Key responsibilities
- Collaborate with the production software team and power architecture team to define architecture and micro‑architecture for various power features.
- Learn how the PMU’s function impacts the system and support silicon debug activities.
- Implement the defined micro‑architecture in RTL design.
Required profile
- Bachelor’s or Master’s degree in Electrical or Computer Engineering.
- At least 3 years of ASIC design experience, preferably with a graduate degree.
- Strong oral English communication for frequent interaction with teams in the USA and India.
- Familiarity with frontend ASIC design.
Required skills
- Frontend ASIC design
- RTL design
- RISC‑V architecture
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NVIDIA
Shanghai
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