Digital Verification Engineer (Graduate)

About the role

Analog Devices is hiring a Digital Verification Engineer to ensure its digital and mixed-signal products behave exactly as specified before silicon. You will take part in the full Metric Driven Verification (MDV) flow across mixed-signal ICs, large-scale SoCs with embedded processors and hardware-software co-designed products, working in an AI-augmented engineering environment where agentic AI tools speed up testbench development, debugging and regression analysis.

Key responsibilities

• Verify planning: analyze specifications to define verification scope, features and coverage goals
• Testbench development: build and maintain block- and system-level environments using SystemVerilog, UVM or C++
• Test and regression: create test cases, run regressions and drive functional and coverage closure
• Debug: investigate failures across RTL, testbench and system boundaries and drive them to resolution with the design team
• Auxiliary verification: support formal verification, directed testing and FPGA-based validation
• AI-augmented engineering: use agentic AI tools to accelerate verification while reviewing and validating their output

Required profile

• Solid understanding of digital logic design and the IC design flow
• Familiarity with SystemVerilog, UVM or C++ and simulation-based verification concepts
• Able to reason about correct behavior and prove it, not just exercise it
• Questions results that look plausible and checks them against the spec or an independent method
• Quick learner, curious and collaborative, with enough English for daily communication and technical documents
• Preferred: Master's degree or above in electronics, microelectronics, computer science, mathematics, physics, automation or similar

Required skills

• Preferred: scripting skills (Python, Perl, Tcl)
• Preferred: hands-on experience with AI coding assistants or agentic development tools
• Preferred: background in AI/ML for edge deployment (inference, quantization, real-time constraints, AI hardware acceleration)
• Preferred: exposure to formal verification, SVA or coverage closure
• Preferred: familiarity with AXI/AHB/APB or other bus protocols and verification IP