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Senior Manager, Digital Design Engineering

analogdevices · ZuChongzhi

New
Senior 🇬🇧 English
RTL design SoC integration Static timing analysis Synthesis CDC/RDC

Job description

About the role

Analog Devices is seeking an experienced, hands-on Senior Digital Design Manager to lead digital IC development for optical control ICs used in AI data center and cloud infrastructure applications. The role combines deep technical leadership with strong team and project ownership, guiding a team of digital designers from architecture definition through RTL implementation, integration, verification support and tape-out.

Key responsibilities

  • Lead digital RTL design for complex IP blocks and chip-top/subsystem integration, and drive architecture and micro-architecture decisions on performance, power, area, timing and reliability.
  • Own digital design execution from architecture through RTL delivery, synthesis readiness, timing closure support and tape-out, with regular design reviews.
  • Define and manage project plans, milestones, schedules, dependencies and risk mitigation, and proactively resolve technical and cross-functional risks.
  • Partner with system, analog/mixed-signal, verification, firmware, physical design, test and product engineering teams for smooth SoC integration.
  • Lead, mentor and grow the digital design team, improve team processes and design methodology, and foster a culture of technical excellence and collaboration.

Required profile

  • M.S. or Ph.D. in Microelectronics, Electrical Engineering, Computer Engineering or a related field.
  • 8+ years of experience in digital IC or SoC design, owning complex IP blocks, subsystems or full-chip designs.
  • Proven experience leading projects and managing engineers, with a track record of delivering through major milestones.
  • Good understanding of verification methodologies, working with verification teams on coverage, debug and sign-off readiness.
  • Excellent communication and stakeholder-management skills, and strong written and verbal English.
  • Comfortable in a fast-paced AI data center product environment; travel required about 10% of the time, first shift.

Required skills

  • Digital architecture, RTL design and micro-architecture definition
  • Mixed-signal SoC integration
  • Digital design flows: synthesis, static timing analysis, clock/reset strategy, CDC/RDC and physical implementation handoff

Questions fréquentes

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Source : ats:workday

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Published 9 hours ago

Expires 1 month from now

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analogdevices

ZuChongzhi