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Senior FPGA Developer

philips · Suzhou

New
Senior 🇬🇧 English
VHDL Verilog SystemVerilog ModelSim Questa SERDES PCIe DDR3 DDR4 Ethernet JESD204 FPGA interfaces memory architectures DMA concepts simulation logic analyzers protocol analyzers Git

Job description

About the role

The role focuses on FPGA architecture, design, verification, and integration for CT platforms. You will collaborate closely with CT control architects, embedded software teams, and global stakeholders to deliver high‑performance real‑time control solutions for next‑generation CT systems.

Key responsibilities

  • Develop and integrate FPGA designs for CT imaging and control applications.
  • Achieve timing closure on medium‑ to high‑complexity FPGA projects.
  • Perform simulation, debugging, and validation using lab instruments such as oscilloscopes, logic analyzers, and protocol analyzers.
  • Work with cross‑functional teams to define interfaces, memory architectures, DMA flows, and register‑based hardware/software integration.

Required profile

  • Bachelor’s or Master’s degree in Electrical, Electronics, Computer Engineering or a related field.
  • 5+ years of FPGA development experience in industrial, medical, communication, imaging or other high‑reliability products.
  • Strong proficiency in VHDL and/or Verilog/SystemVerilog.
  • Hands‑on experience with Xilinx (Vivado, Vitis) or Intel/Altera (Quartus, ModelSim, Questa) toolchains.

Required skills

  • VHDL, Verilog/SystemVerilog
  • Xilinx Vivado/Vitis and Intel/Altera Quartus/ModelSim/Questa
  • FPGA timing closure and synchronous digital design
  • High‑speed transceivers, SERDES, PCIe, DDR3/DDR4, Ethernet, JESD204
  • FPGA interfaces, memory architectures, DMA concepts
  • Simulation, debugging with oscilloscopes, logic analyzers, protocol analyzers
  • Version control using Git
  • Understanding of clock‑domain crossing, reset strategies, metastability

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Source : ats:workday

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Published 1小时前

Expires 1个月后

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philips

Suzhou