Staff Power IC Design Engineer

About the role

Analog Devices is hiring a Staff Power IC Design Engineer for its Shanghai design center. You will develop high-performance power management circuit blocks within ADI's integrated circuits, executing complex power designs from schematic through silicon validation. The role involves close collaboration with global design teams across multiple time zones to support semiconductor process development alongside teams building ADI's next-generation power technologies.

Key responsibilities

• Design and implement power management circuit blocks at the transistor level, including DC-DC converters (buck, boost, buck-boost), LDOs, charge pumps, gate drivers, power stages and protection circuits.
• Apply AI/ML techniques to enhance design automation, optimization and modeling workflows.
• Execute designs from schematic capture through simulation, layout oversight and post-layout verification.
• Perform parasitic-aware simulation, power-stage optimization and design centering across process corners and operating conditions.
• Optimize transient response, loop bandwidth and load regulation through iterative simulation and bench correlation.
• Support silicon bring-up, debug and correlation of measured results against simulation predictions.
• Collaborate with design teams on architecture trade-offs across efficiency, area, EMI, reliability and cost.
• Own block-level and subsystem-level power IC circuits from specification through silicon bring-up, including efficiency optimization, loss analysis, thermal management and reliability assessment.
• Work with global teams to turn customer requirements into circuit specifications, contribute to design reviews and evaluate new process capabilities.

Required profile

• MSEE with 7+ years of power IC design experience, or PhD with 5+ years (BSEE with equivalent depth considered).
• Fluent in Mandarin; strong written and spoken English for cross-site collaboration.
• Ability to collaborate across global, cross-functional teams.
• Preferred: curiosity about AI/ML tools, experience with magnetics modeling and inductor/transformer co-design, knowledge of thermal analysis and EMI/EMC mitigation.

Required skills

• Transistor-level design of high-performance power management circuits.
• Broad understanding of BCD, HV-CMOS and power FET processes, including high-voltage device physics and safe operating area.
• Cadence IC design suite: Virtuoso, Spectre/APS and power-stage simulation environments.
• Control loop design, compensation and stability analysis for switching and linear regulators.
• Tape-out, silicon validation and production release experience.