Senior SOC RTL Integration Engineer

About the role

The Senior SOC RTL Integration Engineer will lead the RTL integration of complex system‑on‑chip products from architecture definition through tape‑out. This role is based in Shanghai and works closely with cross‑functional teams to ensure high‑quality, high‑performance designs.

Key responsibilities

• Lead subsystem and SoC‑level RTL integration for complex SoC products.
• Own and maintain SOC RTL integration, including IP assembly, connectivity, configuration, and design quality checks.
• Define and implement SoC interconnect, clocking, reset, and power architectures to meet performance, power, and functional requirements.
• Collaborate with architects to translate specifications into robust RTL implementations.
• Work with IP, Verification, DFT and Physical Design teams to resolve integration challenges and meet project milestones.
• Drive continuous improvement of integration methodologies, automation flows, and design quality.

Required profile

• 5+ years of ASIC/SoC design and integration experience (senior level).
• Strong Verilog coding skills and solid digital logic design knowledge.
• Deep understanding of AMBA (AXI/AHB/APB) protocols and NoC/NIC architectures.
• Strong knowledge of low‑power design methodologies.
• Experience with industry‑standard EDA tools for lint, CDC, RDC, and low‑power verification.
• Knowledge of automotive/industrial functional safety is a strong plus.
• Excellent communication and cross‑functional collaboration skills.

Required skills

• Verilog
• AMBA AXI, AHB, APB protocols
• NoC/NIC architecture
• Low‑power design methodologies
• EDA lint, CDC, RDC verification tools
• Automotive functional safety knowledge (optional)